[PCIE_DESIGN_EXAMPLE][AGILEX7][QUARTUS25.3.0] - failed at elaboration process

Hi Frederic,

Thanks for reaching out.

The suppress 2732/10000 workaround you applied addresses a separate, known issue with the F-Tile Multi Channel DMA IP simulation in Quartus Prime Pro 25.3 when using Riviera Pro or Siemens Questa*: https://community.altera.com/kb/knowledge-base/why-does-simulation-of-the-f-tile-multi-channel-dma-fpga-ip-for-pci-express-erro/338491

The vsim-3008/vsim-3043 errors you are seeing are not targeted in this workaround.

Could you please let me know if you are using F-Tile MCDMA IP, and which Questa FE simulator version? Additionally, could you disable the PIPE mode in your design example generation if your flow does not strictly require this mode?

Note that, the Table 38. Supported Simulators for F-Tile MCDMA IP in https://docs.altera.com/r/docs/683517/25.3.1/multi-channel-dma-ip-for-pci-express-design-example-user-guide/supported-simulators MCDMA Design Example user guide confirms that the External Descriptor Controller Design Example (Data Mover Only mode) does not support Questa - Altera FPGA Edition and requires the full QuestaSIM instead. Please switch to the full QuestaSIM instead of Questa FE if you are using the F-Tile MCDMA IP.

Thanks.

Best Regards,

Ven