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Ashoo's avatar
Ashoo
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23 days ago

MCDMA IP D2H Queue Reset Failure during Channel Re-allocation

After successfully loading the binary and launching D2H (Device-to-Host) operations on my FPGA, the first channel is allocated successfully and transfers data without issue. However, when I try to al...
Pcie
Ashoo's avatar
Ashoo
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7 days ago

Hi Wincent_Altera​ ,

Thanks for your explanation regarding the queue reset timeout. We will increase the timeout value as suggested.

However, we are currently observing a different issue during runtime testing.

Previously, all channels were working correctly in D2H mode when initialized one by one. But now, during testing of same design and same application with/without timeout added:

  • When we initialize Channel 1 -> it works fine.
  • When we initialize Channel 2 -> it starts reading initially, but after 1-2 seconds, DMA gets stuck.
  • If we stop Channel 1 -> Channel 2 immediately resumes normal operation.

Please provide insights regarding the same.

I have a few questions regarding MCDMA behaviour as well:

  1. How does channel scheduling or balacing work internally in multi channel mode in AVMM configuration? Is there any mechanism and how to configure it, or do we need to manage balancing from software?
  2. Is it possible for one active chanel to starve other channel requests (e.g., due to descriptor fetch or AVMM bandwidth sharing)?
  3. We also observe that during each channel initialization, the queue reset sequence for each new channel initialized takes even more time.

Please provide concrete reasoning.

Regards,
Ashoo

Wincent_Altera's avatar
Wincent_Altera
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6 days ago

Hi Ashoo ,

Based on my understanding..

Question 1 - The behavior where Channel 2 gets stuck when Channel 1 is active, but resumes once Channel 1 stops, is classic evidence of resource contention or starvation. This typically happens at the memory bus (AVMM) or descriptor fetch interface, where one channel monopolizes shared hardware resources, preventing others from proceeding.

Question 2 - MCDMA typically using round-robin for channel access. This can depend on your IP configuration, but in most cases, the arbitration policy is not designed for strict fairness or bandwidth balancing.

Question 3 - As more channels are initialized, each new queue reset takes longer. This is likely due to the reset logic waiting for access to shared hardware (e.g., AVMM, state machines, FIFOs). These delays are aggravated when other channels are active and holding bus resources.

Hope that able to help you to move forward.
I am just trying to share some experience based on what I understand from your issue, do correct me if there is anything I misunderstand.

Regards,

Wincent