JESD204B - which modules can be reused from the example design for a single transceiver configuration?

I was able to create a single transceiver test case using most of the components from the canned example design. Unneeded portions of the control_unit state machine were commented out (I did not need the SPI operations). Obviously, the JESD204B core itself had to be regenerated with my custom parameters. A key piece that does not get updated with the required parameters is the core_pll module. The following link provides a couple of important formulas to determine the proper core_pll settings:

https://www.intel.com/content/www/us/en/programmable/documentation/bhc1447658054961.html#bhc1447657983877

It's disappointing that this key part of the JESD204B design is not handled by the IP generator. The PLL settings and the JESD204B IP are absolutely tied together based on the chosen parameters. You may still see rx_is_lockedtodata, dev_lane_aligned and the rising edge of sync even when the core_pll is configured improperly. Improper core_pll settings are what caused me to see repeated groups of bytes on the RX side.