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Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
22 days ago

F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer

Hello Support, I am using the Agilex 7F Dev Kit with F-Tile configured in Root Port Gen3x4. When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh, the end point se...
Pcie
RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
5 days ago

The F-Tile is RP so it's type1. The CfgWr0 to EP BAR0 with FFFF_FFFFh is for finding the BAR0 size, right? Once the EP BAR0 is enabled, the RP can read/write to that BAR.

Thus you need to set BDF on RP(type1), and enable BAR0 on EP(type0).

 

 

Regards,

Rong

 

Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
4 days ago

Rong,

I recall you the bus access sequence I show you is working with R-Tile. This is exactly the same sequence.

So why It is not working with F-Tile ?

Thank you.
Serge

 

  • RongY_altera's avatar
    RongY_altera
    Icon for Contributor rankContributor
    1 hour ago

    I think you should trigger tx_st_valid.

     

    Regards,

    Rong