Forum Discussion
Serge93
Occasional Contributor
Occasional ContributorF-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer
Hello Support, I am using the Agilex 7F Dev Kit with F-Tile configured in Root Port Gen3x4. When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh, the end point se...
You may need to recheck your design if a given valid is not seen by the IP.
Here is how a F-Tile RP reads another FPGA's VID.
RongY_altera
Contributor
ContributorThe F-Tile is RP so it's type1. The CfgWr0 to EP BAR0 with FFFF_FFFFh is for finding the BAR0 size, right? Once the EP BAR0 is enabled, the RP can read/write to that BAR.
Thus you need to set BDF on RP(type1), and enable BAR0 on EP(type0).
Regards,
Rong
Serge93Occasional Contributor
Occasional ContributorRong,
Can you translate your last sentence in bus access to the RP IP in order I understand what you mean.
Thank you.
Serge
