Forum Discussion
Serge93
Occasional Contributor
Occasional ContributorF-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer
Hello Support, I am using the Agilex 7F Dev Kit with F-Tile configured in Root Port Gen3x4. When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh, the end point se...
You may need to recheck your design if a given valid is not seen by the IP.
Here is how a F-Tile RP reads another FPGA's VID.
RongY_altera
Contributor
ContributorThanks for the detailed info. This is very helpful since checking these reg values manually takes a lot of time.
Are you able to read EP VID and DID, configuration offset 0x0?
Regards,
Rong
Serge93Occasional Contributor
Occasional ContributorHello Rong,
You are welcome.
No I cannot read the EP_VID and EP_DID. When I am doing a read on this register I did not get an answer.
Do you have a Pcie Protocole Analyzer ti check what is produce by tve F_Tile ?
Thanks.
Serge
