Forum Discussion

Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
2 months ago
Solved

F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer

Hello Support, I am using the Agilex 7F Dev Kit with F-Tile configured in Root Port Gen3x4. When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh, the end point se...
Pcie
  • RongY_altera's avatar
    RongY_altera
    1 month ago

    You may need to recheck your design if a given valid is not seen by the IP.

    Here is how a F-Tile RP reads another FPGA's VID.
     

RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 month ago

I'm trying to setup a F-Tile RP test env to check.

Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

Thank you Rong.

Do you need my project ?  I can encrypted it and send it to you if you want ?

  • The sequence I am doing is the following :
    • Using the configuration Bus :
      • Read @82h to get Link Rate and Link width
      • Write 00h at @18h
      • Read @18h to check previous Write
      • Write 01h at @19h
      • Read @19h to check previous Write
      • Write 01h at @1Ah
      • Read @1Ah to check previous Write
      • Write 00h at @1Bh
      • Read @1Bh to check previous Write
      • Write 06h at @04h
      • Read @04h to check previous Write
      • Read @78h to get RP Dev CTRL register
      • Read @79h to get RP Dev CTRL register
      • Read @7Ah to get RP Dev CTRL register
      • Read @7Bh to get RP Dev CTRL register
      • Read @74h to get RP CAP Payload Max
    • Using the Avalon Stream Bus
      • Configuration Write type 0 End Point BAR0 with FFFFFFFFh @10h
        • Wait for completion (Completion received)
      • Configuration Read ype 0 End Point BAR0 @10h
        • Wait for completion (Completion NEVER received.

Please let me know if you need any other information.

Thanks for help.
Serge