Forum Discussion
Occasional ContributorF-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer
You may need to recheck your design if a given valid is not seen by the IP.
Here is how a F-Tile RP reads another FPGA's VID.
Occasional ContributorHello Rong,
Any news, I am blocked now. Can you have the help from another person ?
Thank you.
Serge
ContributorI'm trying to setup a F-Tile RP test env to check.
- Serge93
Thank you Rong.
Do you need my project ? I can encrypted it and send it to you if you want ?
- The sequence I am doing is the following :
- Using the configuration Bus :
- Read @82h to get Link Rate and Link width
- Write 00h at @18h
- Read @18h to check previous Write
- Write 01h at @19h
- Read @19h to check previous Write
- Write 01h at @1Ah
- Read @1Ah to check previous Write
- Write 00h at @1Bh
- Read @1Bh to check previous Write
- Write 06h at @04h
- Read @04h to check previous Write
- Read @78h to get RP Dev CTRL register
- Read @79h to get RP Dev CTRL register
- Read @7Ah to get RP Dev CTRL register
- Read @7Bh to get RP Dev CTRL register
- Read @74h to get RP CAP Payload Max
- Using the Avalon Stream Bus
- Configuration Write type 0 End Point BAR0 with FFFFFFFFh @10h
- Wait for completion (Completion received)
- Configuration Read ype 0 End Point BAR0 @10h
- Wait for completion (Completion NEVER received.
- Configuration Write type 0 End Point BAR0 with FFFFFFFFh @10h
- Using the configuration Bus :
Please let me know if you need any other information.
Thanks for help.
Serge- RongY_altera
Thanks for the detailed info. This is very helpful since checking these reg values manually takes a lot of time.
Are you able to read EP VID and DID, configuration offset 0x0?
Regards,
Rong
- Serge93
Hello Rong,
You are welcome.
No I cannot read the EP_VID and EP_DID. When I am doing a read on this register I did not get an answer.
Do you have a Pcie Protocole Analyzer ti check what is produce by tve F_Tile ?
Thanks.
Serge
- RongY_altera
I think something is mixed here. Most actions should be done to the type1 config register. But the mem space enable should be written to type0 command.
- Read @82h to get Link Rate and Link width
- Write 00h at @18h
- Read @18h to check previous Write
- Write 01h at @19h
- Read @19h to check previous Write
- Write 01h at @1Ah
- Read @1Ah to check previous Write
- Write 00h at @1Bh
- Read @1Bh to check previous Write
- Write 06h at @04h <------------------------to type0 command
- Read @04h to check previous Write
Regards,
Rong
- Serge93
Hello Rong,
All these accesses are done on the configuration space of the RP Pcie directly through the configuration bus.
There is no type 0 or type 1 concern to have.
Thanks.
Serge
- The sequence I am doing is the following :
