Forum Discussion

Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
2 months ago
Solved

F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer

Hello Support, I am using the Agilex 7F Dev Kit with F-Tile configured in Root Port Gen3x4. When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh, the end point se...
Pcie
  • RongY_altera's avatar
    RongY_altera
    1 month ago

    You may need to recheck your design if a given valid is not seen by the IP.

    Here is how a F-Tile RP reads another FPGA's VID.
     

RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
2 months ago

Hi Serge,

 

When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh

>>This doesn't look right. For a BAR test, I think you should use MWr and MRd.

 

Regards,

Rong

 

Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

Hello Rong,

Nice to see you again.

BAR0 in address 10h, is in the Configuration Space not in the Memory Space, so you have to use a Configuration Access. I am using the same access with my Agilex7i-R-Tile board and it is working. So this is very strange it is not working on the Agilex-7F board.

Thanks for help.
Serge