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spte
New Contributor
New ContributorDisplayPort TX IP Core Link Training Abort
Hi All, we are using the Intel DisplayPort TX IP core on Cyclone 10 GX FPGA and we see link training failures with a certain sink (monitor) of our customer. Using a DP aux channel analyzer, w...
ZH_Intel
Frequent Contributor
Frequent ContributorHi Stefan,
Thank you for your reply.
Allow me to clarify with you some of the items below:
1) Could you share with us the design you are using? DPTX only design?
2) Is the design derived from Design Example or custom design? Link controller module from Design example?
3) Could you share with me the setup environment of your project? DPTX -->DP AUX analyzer --> Monitor? are you using DP certified cable?
(Connection setup, type of cable use, cable length, FMC daughter card revision, simple diagram of connection would be helpful)
4) May I know the specification of the sink device?
Hoping to hear back from you so that we can proceed for next step.
Thank you.
Best Regards,
ZH_Intel
