Hello,
To answer your questions, and share some additional insight:
1) These errors are occurring with the Low Latency 100G soft IP, and
2) These errors ALSO occur with the Low Latency 40G soft IP,
3) They do not always occur. Right now, we get this error around 90% of the time. In some cases, the exact same build will sometimes work, but re-running the exact same build (using our automated CI system, so there is no human intervention, and the build environment is the same), causes the build to fail.
4) It doesn't seem to be related to complexity: when we try and compile the design with 100G only, we see this error, but we also see it when we take out our IP.
5) We know that our design routes, and the current build uses comparatively few resources.
6) These problems started occuring after we refactored the code - we suspect this caused a difference in how the inference engine is doing things - but the RTL viewer shows the code is mostly the same.
7) We have confirmed that this is an issue with Quartus 19.4, and Quartus 20.2.
Our latest build compiles if the IP is generated using Quartus 19.4, but the actual build is done by Quartus 20.2. If the entire build is carried out by Quartus 20.2, then we encounter the same issue.
The specific error message consists of a very large number of lines that look like this:
Info (170189): Fitter placement preparation operations beginning
Info (170191): Fitter placement operations beginning
Error (170077): Cannot place the following nodes
Error (170078): Cannot place node "auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric_0|mm_interconnect_0|limiter_pipeline_001|gen_inst[0].core|data1[9]" of type Register cell with location constraints CUSTOM_REGION_X11_Y37_X282_Y432 from Promoted Clock Region File: /
1SX280HU3F50E2VG__/qdb/_compiler/blah/_flat/19.4.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_avalon_st_pipeline_
stage_1920/synth/altera_avalon_st_pipeline_base.v Line: 66
Error (170079): Cannot place node "auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric_0|mm_interconnect_0|rsp_mux|src_payload[2]~40xsyn" of type Combinational cell File: /scratch/fpga-q17/build-dir/fpga/build-tate/build__1SX280HU3F50E2VG__master__full40trx4__cyan-rtm2
.2-ddr-430-g2e4f3f99__2021-09-01-152714296614376/qdb/_compiler/tate/_flat/19.4.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_merlin_multiplexer_191/synth/alt_sld_fab_0_altera_merlin_multiplexer_191_ldk5wsi.sv Line: 152
It includes DSP and ethernet blocks - but the issue we are seeing generally happens when both are in play. However, we've seen this failure when we compile with only usually works, however, if I include the Ethernet and our DSP blocks, it fails fitting.
If I compile a very, very, simple design, then it sometimes works. However, if I compile a design with additional user logic, I then get the errors above. We spent the day porting the code to quartus 20.2 from 19.4, but our CI system still shows these kind of errors. I've looked at the KB and forum posts, and it seems similar to the following:
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2018/why-does-my-dsp-design-fail-during-fit-with-error-170079---canno.html
and
https://community.intel.com/t5/Intel-Quartus-Prime-Software/Seeking-a-solution-to-Quartus-Prime-19-2-fitter-error-170079/td-p/704677
In the second post, it suggests that this is an errata with Quartus itself. Can you confirm that there haven't been any similar issues in Quartus 20.2?
Best Regards,
New Contributor
