Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorquestions about clock frequency in DSP-BUILDER
Hi everyone:), I wish to use a really low clock frequency in DSP builder, say about 100HZ, it does not need to be very accurate. since PLL won't work. Here's my idea: 1. in VHDL, it could ...
Altera_ForumHonored Contributor
Honored ContributorIf you are using dsp builder then please remember that the preferred way is using the primitives (if available, e.g., counter, etc.) first... rather than putting own code...
About such a low frequency clock you first need to know that what is the default base clock in your design and how to change it.. Of course it has limits (both highest and lowest possible)... using 'Clock' block from "Altera DSP builder block set"... then further lower it down using a counter.... Hope it works...
