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Hi everyone:),
I wish to use a really low clock frequency in DSP builder, say about 100HZ, it does not need to be very accurate. since PLL won't work. Here's my idea:
1. in VHDL, it could be easily made by a counter and a reverse process, so I tried to import VHDL to the simulink, yet there's another problem: how to specify the clock signal in DSP builder to a signal inside the design ?:(
2.If the first method doest not work, maybe a "enable" pulse generator is ok. is it like that I have to put some flip-flops in the circuit ? my design has many freedback paths, I'm not sure if the flip-flops would harm the feedback property.
It there any reference design for a low frequency clock in DSP builder? that would be great.
Sorry for the poor English, I would really appreciate any discussion
Tony
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the second method would take extreme simulation time in simulnk
What if I buy a low-f oscillator as clock signal, does FPGA need a minimum frequency requirement for clock signal ?
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