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In EMI Page 203 Table 1-19 have following description:
each address and control pin routes from the fpga (single pin) to all memory devices must be on the same side of the fpga. How should I explain it?
For example,i use bank1-bank4 of EP3C40F484 to interface 64bit DDR2,can i use the remaining IO ports of all bank1-bank4 as address and control pin ?
thanks!
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See table 8-1 in the Cyclone III Handbook (section 8). There seems to be no way to use one DDR2 controller to handle more than 36 DQ lines in a Cyclone III. By "side" they mean one of the four sides, comprised of two I/O banks. Use the Quartus II pin planner to see what the I/O banks look like -- and there is even a finer structure to the pin placement than "side" (see "DQ groups").
You could use two separate DDR2 controllers on two different sides of the chip to handle two separate 32bit DDR2 ram chips. But they would be separate and might not stay in sync.
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