Honored Contributor
Honored ContributorI'm not exactly familiar with the cyclone device you're using, but I assume the clue is the same as with the stratix I'm currently using:
The requirements of the DDR pins being on "one side" of the FPGA originates from clock distribution requirements: The IP make use of the PLL located in the middle of a side to have clock skew and signal delays low as possible. It would not be helpfull to distribuite your DDR controller over the whole FPGA. Yes, you can use the remaining IO as address etc.. Make sure the pins can support the required function, i.e. differential outputs need to be on pins that support this (e.g. DQS/DQSN). Hope this gives some starting points... Regards, Peter
