Honored Contributor
Honored ContributorWhat frequency do the LVDS signals operate at?
Assuming the signals are routed differentially, and the impedance of the boards and backplane does not generate reflections, the LVDS will have no issue running up to 100MHz+. I use 250Mbps LVDS over VHDCI cables that are 4ft long (using Stratix II FPGAs). If your backplane is shorter than 4ft, you will be ok. Longer than that, and you will need to check things work. If the control board sends the clocks point-to-point as well as the data, then you only need to configure the control board correctly. Your device boards will have a clock-to-data expecation, eg., centered or edge aligned. All you need to do is have the host transmit data and clocks in that format. If the control and device boards all use FPGAs for the LVDS interface, then you can use the ALTPLL_RECONFIG to determine how much of an eye pattern opening you have. You do not need external test equipment, though it would be good to look at the waveform shape and differential swing. Cheers, Dave
