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JET60200's avatar
JET60200
Icon for Contributor rankContributor
4 years ago

question about “ A10SOC as PCIE RC ”

hello expert, We plan to start an “ A10SOC PCIE RC” design, while the peer side PCIe EP is a "pcie subcard w/ (gen3x8)". Our target is to run Linux System on this A10SOC （HPS）, and use HPS AR...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


It's possible to use Arria 10 PCIe HIP as root complex but the reference design for it is limited as typically we promote FPGA for PCIe EndPoint application.


So far I can only find below A10 PCIe RC reference design using HPS but it's targeting till PCIe Gen2 x8 only.


Nevertheless, fell free to check it out.


Thanks.


Regards,

dlim


  • JET60200's avatar
    JET60200
    Icon for Contributor rankContributor
    4 years ago

    Thanks @Deshi_Intel for quick response , Will check the details

    best regards