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bjwinter's avatar
bjwinter
Icon for New Contributor rankNew Contributor
4 years ago

Quartus Prime v18.1 : Arria 10 DDR4 Controller & PHY

This error appears when I attempt to Synthesize a design containing a DDR4 Controller and PHY combination in an Arria 10 target. Error (129029): Input port RZQIN on atom "ddr4:u_ddr4|ddr4_altera_em...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Bradley,

You need to make a connection in your top level design for the instances.

  • OCT
  • Reset

The EMIF_pll_ref_clk cannot be hooked up to internal PLL pin.

It's must be connected to external pin.

There are several dq pins that are not fit in the design.

So I let the Quartus to Auto Fit the signals pin location.

I will share the design that I've edited.

I hope it's working just like you wish.

Thanks,

Adzim