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Dongwei939's avatar
Dongwei939
Icon for New Contributor rankNew Contributor
3 years ago

Quartus Prime Pro 22.4 F-tile error: Error(21842): Support logic cannot be generated because IP

I tried to set the F-tile:

  • FHT
  • Number of PMA lanes: 4
  • System PLL
  • PAM4
  • PMA width: 128
  • Disable RS-FEC

I use the example "FHT PAM4 4 400G 4 PMA lanes RSFEC 544/514" in F-tile PMA/FEC Direct PHY Intel FPGA IP. But, I want to disable the RS-FEC. I only click the "Enable RS-FEC", this shuts down the RS-FEC. And I open the example_design -> rtl -> param_desines1.iv, comment the "`define RSFEC_TESTWRAP 1". Then, Quartus 22.4 starts compiling.

At the Logic generation, I get errors.

Error (21842): Support logic cannot be generated because IP components used in the design have conflicting settings
Error (21843): Conflict 0 ----------------------------------------------------------------
Error (21843): Rule: gdra_gdr_barak_quad::bk_rxbit_rollover_lane3_rule @ gdr.z1577a.u_barak_quad
Error (21843): ((gdr.z1577a.u_barak_quad.bk_rxbit_rollover_lane3 -> u0|example|dphy_hip_inst|persystem[0].perxcvr[0].fht.x_bb_f_bk.bk_rxbit_rollover)>=(gdr.z1577a.u_barak_quad.bk_rx_lat_bit_for_async_lane3 -> u0|example|dphy_hip_inst|persystem[0].perxcvr[0].fht.x_bb_f_bk.bk_rx_lat_bit_for_async)) || gdr.z1577a.u_barak_quad.powerdown_mode == TRUE
Error (21843): Rule: gdra_gdr_barak_quad::gdr_barak_quad_avmm_cfgcsr_power_down_rule @ gdr.z1577a.u_barak_quad
Error (21843): gdr.z1577a.u_barak_quad.powerdown_mode == FALSE || (gdr.z1577a.u_barak_quad.refclk1_freq -> u1|systemclk|x_hip|gen_fht_bb_[0].enabled.refclk_inst.freq) == 1
Error (21843): Input variables:
Error (21843): user.bb_f_bk[0] -> u0|example|dphy_hip_inst|persystem[0].perxcvr[0].fht.x_bb_f_bk
Error (21843): bk_rx_lat_bit_for_async == 5248
Error (21843): bk_rxbit_rollover == 5152
Error (21843): is_used == TRUE
Error (21843): location == BK3
Error (21843): user.bb_f_bk_refclk[0] -> u1|systemclk|x_hip|gen_fht_bb_[0].enabled.refclk_inst
Error (21843): freq == 156250000
Error (21843): is_used == TRUE
Error (21843): location == BK_REFCLK1
Error (21843): Conflict 1 ----------------------------------------------------------------
Error (21843): Rule: gdra_gdr_barak_quad::bk_rxbit_rollover_lane3_rule @ gdr.z1577a.u_barak_quad
Error (21843): ((gdr.z1577a.u_barak_quad.bk_rxbit_rollover_lane3 -> u0|example|dphy_hip_inst|persystem[0].perxcvr[0].fht.x_bb_f_bk.bk_rxbit_rollover)>=(gdr.z1577a.u_barak_quad.bk_rx_lat_bit_for_async_lane3 -> u0|example|dphy_hip_inst|persystem[0].perxcvr[0].fht.x_bb_f_bk.bk_rx_lat_bit_for_async)) || gdr.z1577a.u_barak_quad.powerdown_mode == TRUE
Error (21843): Rule: gdra_gdr_barak_quad::gdr_barak_quad_avmm_cfgcsr_power_down_rule @ gdr.z1577a.u_barak_quad
Error (21843): gdr.z1577a.u_barak_quad.powerdown_mode == FALSE || (gdr.z1577a.u_barak_quad.bk_rxbit_rollover_lane3 -> u0|example|dphy_hip_inst|persystem[0].perxcvr[0].fht.x_bb_f_bk.bk_rxbit_rollover) == 0
Error (21843): Input variables:
Error (21843): user.bb_f_bk[0] -> u0|example|dphy_hip_inst|persystem[0].perxcvr[0].fht.x_bb_f_bk
Error (21843): bk_rx_lat_bit_for_async == 5248
Error (21843): bk_rxbit_rollover == 5152
Error (21843): is_used == TRUE
Error (21843): location == BK3
......

Please help me check the source of the problem, is it a bug?

Regards,

2 Replies

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,


    If you select any of the four available Example Design Options, but change the F-Tile PMA/FEC Direct PHY Intel® FPGA IP settings in the GUI thereafter, the example design generated does not follow the changed settings for the F-Tile PMA/FEC Direct PHY Intel® FPGA IP. The example design generation only takes the Example Design Options listed in Example Design Generation Options. Any other changes that you make to the F-Tile PMA/FEC Direct PHY Intel® FPGA IP settings are not applied during example design generation.


    Clicking Generate Example Design completes the IP Generation and Support-logic Generation stages of the Compiler.


    For more info please refer to the below link.


    https://www.intel.com/content/www/us/en/docs/programmable/683872/22-4-4-3-0/example-design-generation.html


    Hope this will resolve your issue.


    Thank you

    Kshitij Goel


  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,


    As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Thank you

    Kshitij Goel