Quartus Prime Pro 22.4 F-tile error: Error(21842): Support logic cannot be generated because IP

Hi,

If you select any of the four available Example Design Options, but change the F-Tile PMA/FEC Direct PHY Intel® FPGA IP settings in the GUI thereafter, the example design generated does not follow the changed settings for the F-Tile PMA/FEC Direct PHY Intel® FPGA IP. The example design generation only takes the Example Design Options listed in Example Design Generation Options. Any other changes that you make to the F-Tile PMA/FEC Direct PHY Intel® FPGA IP settings are not applied during example design generation.

Clicking Generate Example Design completes the IP Generation and Support-logic Generation stages of the Compiler.

For more info please refer to the below link.

https://www.intel.com/content/www/us/en/docs/programmable/683872/22-4-4-3-0/example-design-generation.html

Hope this will resolve your issue.

Thank you

Kshitij Goel