RicardoCOccasional Contributor2 years agoQuartus 24.2 CXL ED support for DK-DEV-AGI027-RA Hi, The R-TIle Intel FPGA IP for Compute Express Link (CXL) Example Design in Quartus 24.2 does not provide an option for DK-DEV-AGI027-RA as a development board. How can the ED be generated for th...Show More
Recent DiscussionsAbout Design Limitations and Known IssuesAbout Dual Simplex for Agilex 3Where is High Speed Transceiver Demo Design in FPGA Wiki ?Can't find Agilex 7 M I/O PLL Reconfiguration Design ExampleEnabling DFE Adaptation on Cyclone 10 GX