Forum Discussion
ltazz1
New Contributor
5 years agoThank you for the clarification.
I am reverting back on Q18.1 to use PCIE, just in case, to avoid any problem.
I was trying to compile some example of the DE4 dev board but internal timing of the PCI IP are failing:
pcie|pcie_internal_hip|stratix_iv.stratixiv_hssi_pcie_hip|coreclkout setup slack -1.194
Is something that can be ignored?