Qsys pcie ref design - read and write descriptors

I have not yet tried it but...

1. Has anyone modified the mSGDMA to distinguish between a read and a write descriptor?

>> it is possible to have set of mSGDMA for each dedicated direction.

>> just make 3 components for each directions, read master, write master, and dispatcher

2. Should I just rename DMA_write to DMA_read (and vice versa) in the software program and ditch the slavewrite and slave reads that seem to be transferring expected data?

>> as noted above, you need to have 2 sets.

3. If I'm using the DMA read function, should I just set the write address to an unused memory space on the DDR3?

>> as far as I know, the DDR3 does not accept 2 access at a time.

>> it means, only read or write operation can be done at a time.

>> if write happens after the read, any address should be fine.