Qsys PCIe core fails timing

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This tells me that the PCIe Hard IP master may have been doing something wierd. And the NIOS II running maybe changed the state of how the Avalon MM interconnect was behaving such that the PCIe Avalon MM master , BAR1, was getting stale data back on reads.

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To test your theory, you could try inserting a pipeline bridge between the NIOS II and the PCIe. The bridge would be pointless, but it might change the Avalon-MM internal pipelining sufficiently to "change" your error.

Cheers,

Dave