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Altera_Forum
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13 years ago

Qsys PCIe core fails timing

Hi, I've been analyzing the Altera PCIe Hard-IP cores. I started off with the Qsys PCIe code, since it had the simplest interface. Here's the test setup: * Quartus 11.0, 11.1sp1, 11.1...
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Altera_Forum
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12 years ago

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My update on this....

As well as not meeting timing I had a problem with an Error 10232 when I

tried building a Quartus 11.0 Qsys system in Quartus 11.1sp2.

The solution to this was to move a PIO output in the Qsys memory map, this not only cleared the error but from that point on all my designs have been meeting timing.

:confused:

Nial

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Hi Nial,

Could you

please explain the statement "move a PIO output in the Qsys memory map", is it specific to your design? I also have the issue of timings fail when using 100MHz clock for gen 1, X1 link in Cyclone IV GX devices.

Thanks,

laland