Qsys PCIe core fails timing

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I would like to reproduce Your PCIe analysis, but on Cyclone IV GX FPGA Development Kit.

Please advise - what should be modified in the contents of altera_pcie.zip so that, it could be used with Cyclone IV GX FPGA Development Kit?

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Look at the code. Its already split into designs for two boards. It should be fairly easy to figure out how to change it for use on a new board.

The main thing you need to change is the top-level pin assignments, i.e., create a template for your kit (I don't have that kit, so haven't created a top-level design for it).

You can use the same Qsys systems since they both use on-chip resources. The only difference between the Stratix and Cyclone kits were the number of lanes. I think your kit has x4, so you can copy either the Cyclone starter kit x1 design or the Stratix x4 design, or you can just follow the procedure in the document to create your own Qsys instance, and then look at the existing code to see how to connect it to the top-level template.

Cheers,

Dave