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Altera_Forum
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13 years ago

Qsys PCIe core fails timing

Hi, I've been analyzing the Altera PCIe Hard-IP cores. I started off with the Qsys PCIe code, since it had the simplest interface. Here's the test setup: * Quartus 11.0, 11.1sp1, 11.1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I've described the design process and have written automated synthesis scripts (making it easy for anyone to reproduce my results):

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie_analysis.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_pcie_analysis.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_pcie.zip)

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Hello, Dave!

I would like to reproduce Your PCIe analysis, but on Cyclone IV GX FPGA Development Kit.

Please advise - what should be modified in the contents of altera_pcie.zip so that, it could be used with Cyclone IV GX FPGA Development Kit?