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So far I haven't had a problem negotiating at x4 gen2. My design is a custom PCB with different clock sources to the dev board. The reconfig_pll is driven by an external free running clock at 125Mhz on LVDS pins. Also the design passes timing - perhaps this was cleaned up in QuartusII v12.
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I'll have to re-run these tests in 12.1 and see if anything has changed.
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I'm not in a position to measure the reconfiguration time as no chipscope support for my cable.
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Careful, your Xilinx is showing ;)
If you have a USB-Blaster cable, then SignalTap should work fine.
Cheers,
Dave
Honored Contributor
