New Contributor
New ContributorFinally someone who answers my question. Thank you sstrell.
But your answer is not very good for my problem.
As I understand, enabling the waitrequest-Signal in Tristate-Controller disables the "automatic communication" between PCIe-Core and Tristate-Controller and I have to handle it with my slave device (the DP-RAM).
But the DP-RAM can't control this communication. It needs specific timing to be able to do anything. But this Timing is destroyed. It's a very slow Device (ISA like bus) which can't even recognize the Signals coming from PCIe-Core and therefore isn't able to set the waitrequest properly.
Although, when I assert the waitrequest-Signal, the Tristate-Controller deasserts its Signals from bus. But I just need them to stay and pause.
I just need a Signal to pause the Tristate-Controller and not to detach it from the bus.
The second problem is that the Signal coming from my Slave is only asserted when a collision occured. Normally the Signal is not asserted and I need the Timing configured as shown in my previous post.
Is there a Signal somewhere, where I can just pause the Tristate-Controller but keep its timing if there is no such "Pause"-Signal? How could I achieve something like that without writing my own Tristate-Core?
