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SDost's avatar
SDost
Icon for New Contributor rankNew Contributor
6 years ago

QSYS Generic Tristate Controller. Issues on Waitrequest-Signal

Hello, I want to biuld an interface to a very special dual-port RAM. I already can access it with the Generic-Tristate-Controller to read and write Data. The timing is correct. But the RAM has a s...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

I'm not sure if this is the issue, but when you enable waitrequest, that means your system is relying on manual assertion and deassertion of waitrequest back to the master (the PCIe in this case) instead of the Platform Designer system handling it automatically. As such, as soon as waitrequest is released by your RAM, it is released back at the PCIe interface, which may be why you're seeing such shorter signal durations. If you want to manually control waitrequest in this way, look at the Read Wait Time parameter to control how long after waitrequest is released that a read should actually take place. See section 3.5.3 of the Avalon spec as well: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/archives/mnl_avalon_spec-18-1.pdf

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