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SDost's avatar
SDost
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6 years ago

QSYS Generic Tristate Controller. Issues on Waitrequest-Signal

Hello, I want to biuld an interface to a very special dual-port RAM. I already can access it with the Generic-Tristate-Controller to read and write Data. The timing is correct. But the RAM has a s...
SDost's avatar
SDost
Icon for New Contributor rankNew Contributor
6 years ago

Hello,

The FPGA is acting as a PCIe to Dual-Port-RAM bridge.

The Generic Tristate-Controller is a Avalon MM Slave and directly connected to the PCIe Hard-IP.

Connections and configurations of the QSYS-System are shown in the added pictures. The Signal-Polarities are active high because I invert the needed signals outside the QSYS-System.

The clock of the Controller is provided by PCIe-Hard-IP (pcie_core_clk) and should be 125MHz afaik.

Any more Informations required?