QSYS amm interconnect delay with EMIF (Arria 10)

Hi Adzim,

Sorry for late response, in fact I could resolve the timing issue while keeping signaltap, this was due to the trigger clock which was set to "DDR4A_REF_CLK" (reference clock input for EMIF) instead of the emif_usr_clk of EMIF. Since these have both the same frequency, I have troubles understanding why using the dedicated ref clk in signaltap generated timing errors ? If you have any insight about this, you're welcome.

I will close the topic after this, thanks again for help !