QSYS - Clock sensitiveness

It's not really "times x" because the DRAM latency only intervenes on the cycles where the CPU accesses RAM. For each instructions it will be at least once to read the instruction itself, and one or several times for the data accesses, depending on the instructions (I don't remember right now if some Nios2 instructions can do several data accesses in the same instruction). The latency itself will vary from access to access, especially depending on how far the new access is from the old one. The DRAM datasheet should give more detailed values but it can be a bit cumbersome to figure out. Using instruction and data caches on the CPU will dramatically increase performance.