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Altera_Forum
Honored Contributor
Honored ContributorQSYS - Clock sensitiveness
Hello together! I recently started using soft-cores in FPGA application. The last few days I spend some time to make investigations regarding to the NIOS-II clock sensitiveness (frequency and d...
Altera_ForumHonored Contributor
Honored ContributorThank you for the detailed information, very helpful!!!
--- Quote Start --- ...Then when you say that you counted the cycles using the debugger, was it when stepping through C code or assembly? One step in the C code could be several assembly instructions. If you don't have instruction or data cache you also need to take into account several clock cycles due to the DRAM latency... --- Quote End --- I stepped through in assembly. So that leads to 12 instructions per while loop times 6 cycles per instructions times x cycles due to DRAM latency. (by the way: x is approximately 2.5) I have the feeling that i basically understand the delay, thank you again. Best regards Stefan
