Altera_ForumHonored Contributor8 years agoprotected altera_xcvr_atx_pll_ip_inst Dear All, Today i built the testbench http://www.alterawiki.com/wiki/single_port_ll_ethernet_10g_mac_with_1588_using_native_phy_design_example, in ModelSim. It compiled fine until : # Loa...Show More
Recent DiscussionsF-Tile xcvr placement on DK-DEV-AGF023FAMAX10 TSE reference designCyclone-V SCFIFO with M10K/MLAB memory - adding ECCConstraints not being picked for DCFIFOCyclone 10 GX IBIS-AMI models