Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Problems with FFT Testbench

Hi All, I'm relatively new to FPGA programming, and as a part of a larger project, I am designing a FFT hardware solution to convert a live audio signal into frequency and amplitude pairs (but ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

sink_ready is an output signal of the FFT function. I don't know why you think things work better when you force a value to it. What I know is that you should only read the value of this signal, in order to know if FFT is ready to accept new input data. You initiate the input data transfer by just asserting the sink_valid signal. When both sink_ready and sink_valid are asserted and you also assert sik_sop for one cycle the FFT can start fetching the inputs.

Providing some more details would also be useful.