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Altera_Forum's avatar
Altera_Forum
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14 years ago

Problems with FFT Testbench

Hi All, I'm relatively new to FPGA programming, and as a part of a larger project, I am designing a FFT hardware solution to convert a live audio signal into frequency and amplitude pairs (but ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

My testbench does include this function, I've attached the testbench file, but the relevant code sections are as follows: 


  //sop and eop asserted in first and last sample of data
  always @ (posedge clk)
  begin
    if (reset_n == 1'b0)
      cnt <= 0;
    else
      begin
        if (sink_valid == 1'b1 & sink_ready == 1'b1)
	  begin
             if (cnt == fftpts_array - 1)
               cnt <= 0;
             else
               cnt <= cnt + 1;
          end
      end
  end

and 


   // generate start and end of packet signals
   assign sink_sop = (cnt == 0) ? 1'b1 : 1'b0 ;
   assign sink_eop = ( cnt == fftpts_array - 1 ) ? 1'b1 : 1'b0;