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Altera_Forum's avatar
Altera_Forum
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14 years ago

Problems with FFT Testbench

Hi All, I'm relatively new to FPGA programming, and as a part of a larger project, I am designing a FFT hardware solution to convert a live audio signal into frequency and amplitude pairs (but ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hey, it seems like your troubles are not so hard..

I noticed that sink_sop is always high. It must be asserted only for one cycle, the cycle you provide the 1st input to the fft. Then during the last input you also assert sink_eop, which seems to be always low. Keep both signals low else.

Hope it helps..