Problems with FFT Megacore of Variable Streaming Floating Point Architecture

I just tried to lower the clock frequency to 25 MHz, but it gives me back the same response. QSYS tells me I cannot lower it anymore since the debug module I'm using works at clocks faster then 20 MHz.

Maybe some other informations could be useful for you to help me: I've set my FFT core for a maximum length of 1024 and for input and output sequences in natural order. I'm using a couple of SG-DMA in my QSYS system for writing to and reading from Avalon Streaming interface: for both SGDMA cores, data width is 64 bits (to accomodate real and imag 32-bits wide FFT data) and I've enabled automatic byte swap (bursting and unaligned transfers are disabled instead).