Forum Discussion
Deshi_Intel
Regular Contributor
6 years agoHI Frank,
Have you reviewed your design to ensure there is no timing violation in Quartus timequest analysis that may affect the data transfer ?
After you confirmed your design timing is clean, then you can further isolate whether the issue is with Ethernet MAC or PCIe by using other method to read back Ethernet MAC register value like JTAG master or RTL state machine access or NIOS access.
Thanks.
Regards,
dlim