Problema with ip_compiler for PCI express under QSYS

Hi ramon_garcia,

That is the data rate you place in? The socond 125Mhz seems valid though :p

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Under qsys, if I insert a component "ip_compiler for PCI Express" , when generating HDL the following errors appear:

Error (114000): Time value Mbps Mbps and time unit are illegal

Error (114000): Time value 125.0MHz MHz and time unit are illegal

My FPGA is a Cyclone IV GXI am using Quartus II 15.0.1

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Mind share further on the configuration that you are using? I tried with my Quartus II 15.0 and seems like no issue generating the HDL.

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Mind share further on the configuration that you are using? I tried with my Quartus II 15.0 and seems like no issue generating the HDL.

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I can reproduce the problem by inserting the component "IP compiler for PCI Express" (the only one available for PCI Express for a Cyclone IV) with the default settings. That is, start with a clean design in QSYS (only the default clock), insert IP Compiler for PCI Express, and click "Generate".

I am using Quartus II 15.0.1 for Linux, but I had the same problem with Quartus II 14.0 and 14.1

Finally, I found the reason for this problem.

It is a bug in the Linux version.

Under Windows, it works perfectly.

So I have to switch development to Windows.