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are you referring to analogue signal passed through an ADC?
Once a signal is sampled into digital domain then the frequency range of digital domain is 0 ~ Nyquist and anything more than Nyquist would have already aliased unless there was anti alias filter.
Your FIR should pass the signal and remove noise from edge of signal to Nyquist and it should be sampling at ADC rate.
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Analogue Signal which passed through the ADC into the FPGA is High frequency and Weak amplitude，
so the ADC rate is required high frequency ,
but in FPGA , through processing （digital lock-in amplifier） ，then I need a low-pass FIR filter , so the sampling frequency can't be set too high ,
then the output waveform of the FIR shake up and down .
for example :
1. set the FIR parameter : Fs=1KHZ , Fc=50HZ(Fs < 2*input signal)
input signal ： 1KHZ+1HZ
output signal : 1HZ
but the output signal waveform shake up and down , seems like there are some other low frequency signal !
2. set the FIR parameter : Fs=5KHZ , Fc=200HZ (Fs > 2*input signal)
input signal ： 1KHZ+1HZ
output signal : 1HZ
but the output signal waveform is normal and don't shake .
I’m confused , looking for your reply and thanks a lot !
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