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MSenk1's avatar
MSenk1
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6 years ago

Problem with EMIF IP and the related clocks in the .sdc file

I have instantiated a EMIF IP in Quartus 19.4. Alle emif clock are generated as the timing analyser shows (see attachment. But when I set a false path in the .sdc file for such a clock I get the fo...
MSenk1's avatar
MSenk1
Icon for New Contributor rankNew Contributor
6 years ago

Hello,

I'm using a Cyclone 10 GX with Quartus Pro.

The clock I'm talking about is the 'usr_clk'; which is connected to the Avalon MM slave side , not to the dram hardware side.

The 'usr_clk' is connected to one side of an asynchronous FIFO. The other side of the FIFO is connected to another clock. There are a few signal like aclr and rdreq of the FIFO which have clock crossing signals.

I have to set false paths or asynchronous clock groups in order to get a reasonable timing.

How could I achieve this?

Do you have any idea?

Mike