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xalverti's avatar
xalverti
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Problem with CXL IP Design Example Type 3 on DK-DEV-AGI027RBES

Hi, We are using Quartus 24.1 to compile the type 3 ddr memory design example for the board and program the FPGA using the following guide: Agilex™ 7 R-Tile Compute Express Link* (CXL*) FPGA IP Des...
Cxl
  • xalverti's avatar
    xalverti
    2 years ago

    Hi again,

    The problem was on the PCIe slot on the server side.

    We replaced our card and the problem was fixed.

    For anyone facing the same problems, we had to check the x16 slot with other devices to identify the lane drop issue in BIOS.

    CXL IP designs apparently are note recognized in BIOS as PCIe devices even when the design is working -- the corresponding PCIe slot always shows the message "Link did not train" -- as if nothing is attached on the slot.

    Thank you for your help,

    Chloe

xalverti's avatar
xalverti
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi,

  • I set all switches to the values you state above that however do not match the "(CXL*) FPGA IP Design Example User Guide", and I set all device configuration values of the cxl design to the ones found in the devkit examples.
  • Yes I have compiled and run the PCIe Gen5 example design and it trains successfully and the card is found via "lspci".

Best,

Chloe