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xalverti's avatar
xalverti
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Problem with CXL IP Design Example Type 3 on DK-DEV-AGI027RBES

Hi, We are using Quartus 24.1 to compile the type 3 ddr memory design example for the board and program the FPGA using the following guide: Agilex™ 7 R-Tile Compute Express Link* (CXL*) FPGA IP Des...
Cxl
  • xalverti's avatar
    xalverti
    2 years ago

    Hi again,

    The problem was on the PCIe slot on the server side.

    We replaced our card and the problem was fixed.

    For anyone facing the same problems, we had to check the x16 slot with other devices to identify the lane drop issue in BIOS.

    CXL IP designs apparently are note recognized in BIOS as PCIe devices even when the design is working -- the corresponding PCIe slot always shows the message "Link did not train" -- as if nothing is attached on the slot.

    Thank you for your help,

    Chloe

WZ2's avatar
WZ2
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Sorry for the miss, for RBES, sw4 should be off off on off

xalverti's avatar
xalverti
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

If you see our first post you will read that we have tried this already.

If we go with off/off/on/off we get a jtag chain error. If we go fro off/off/off/off we have the errors you see above.

Also please keep in mind that it seems that for CXL IP designs the switches are not the same as the user guide.

We are following this guide --> Agilex™ 7 R-Tile Compute Express Link* (CXL*) FPGA IP Design Example User Guide version 1.12 for quartus 24.1.

Please give us some advice how to solve this.

Chloe