--- Quote Start ---
Did you connect the VCCA_PLL_x Pins directly to 1,2V Core supply or as Altera recommends via an inductor (ferrit) and some decoupling caps ?
As you use q QFP package, what about your layout ?
Do you have an impedance controlled powersupply ?
As your clock is 27x4=108 MHz you must take at least the 3. harmonic = 324MHz into consideration that your power supply will have a low Z up to 324MHz to control the voltage ripple
Are the traces vor the PLL power supply very short, directly connected to the power supply or are they close to traces with noise ? this would lead to a modulation and might be the source of your unstable DPLL
What speed grade do you use ?
the output of your pll is connected to a dedicated clock pin "PLL?_OUTp" ?
--- Quote End ---
I think the layout is the most possible reason, I didn't consider these in my PCB board. And I didn't connect the output pll to the pin "PLL_out", is this necessary? Thank you
Honored Contributor
