problem of adding custom component in SOPC

I think there are a couple of flaws in your code

Issue# 1:

As I said before, your code increments the counter on each clock pos edge whenever bit6 of input port is asserted.

Now, what's clk frequency? If this is in the kHz or MHz range you will indeed get random numbers from the counter: I don't think you could keep the switch pressed for a single clock period! You'd rather get thousands of counts for every push, even if you are very very fast.

Issue# 2:

IMHO, using out and readdata registers in that way is not good.

Replace = with <= for register assignments: e.g. out <= readdata;

See http://en.wikipedia.org/wiki/verilog for explanation of difference.

I guess in this 2 registers case, the = assignment is logically and syntactically correct but is not exactly synthesizable: that's why the simulation works but the real system doesn't.

Apart this, I'd simply remove the 'out' register; readdata is enough.

Example:

(last is used to keep trace of previous pushbutton status and trigger the count only once)

output reg [ 7: 0] readdata;

input clk;

input [ 7: 0] in_port;

reg last;

always @ ( posedge clk )

begin

if ( in_port[7] == 0 )

readdata <= 8'b0;

else if ( in_port[6] and ~last) // count only if switch has been pushed right now

readdata <= readdata + 8'b1;

// no need for else statement; everything is unchanged

last <= in_port[6];

end