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Pramod_p's avatar
Pramod_p
Icon for New Contributor rankNew Contributor
4 years ago

Problem in download bitstream on Stratix 10 MX board

Hi, I am trying to work with the following design example. https://fpgacloud.intel.com/devstore/platform/18.1.0/Pro/pci-express-gen3-x16-avmm-dma-with-hbm2-memory-reference-design/ I am ab...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


If you look at the user guide, you will observed that the HBM can only support burst count of 1. Below is the information from the document.


Burst length adaptation


The Gen3 x16 IP Write Data Mover (WRDM) and Read Data Mover (RDDM) Avalon-MM interfaces are bursting masters that issue Read/Write transactions in burst mode (the maximum burst count supported is 8). However, the HBM Controller AXI4 slave only supports single-burst transfers (burst length of 1). To resolve this, the maximum burst size in the Avalon-MM clock crossing bridges is set to 1.


  • Pramod_atintel's avatar
    Pramod_atintel
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi John,

    Can you point me to an example where burst count greater than 2 is supported ?