Forum Discussion

New Contributor

4 years ago

Problem in download bitstream on Stratix 10 MX board

Hi, I am trying to work with the following design example. https://fpgacloud.intel.com/devstore/platform/18.1.0/Pro/pci-express-gen3-x16-avmm-dma-with-hbm2-memory-reference-design/ I am ab...

Pramod_atintel

New Contributor

4 years ago

Hi John,

Yeah, I have checked that PCIe IP is sending the signals to HBM controller inputs.

Wanted to check with you:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an881.pdf

the design example above, can the design be made to work with burst count > 1.

Will the design work if increase the burst capability of clock crossing bridge and HBM controller ?

Forum Discussion

Problem in download bitstream on Stratix 10 MX board

Recent Discussions

PCIe Enumeration Failure for CXL IP

Can't generate F-Tile Ethernet Hard IP Design Example

Agilex 7 slew rate reconfiguration

Constraints not being picked for DCFIFO

Cyclone 10 GX IBIS-AMI models