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Pramod_p's avatar
Pramod_p
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4 years ago

Problem in download bitstream on Stratix 10 MX board

Hi, I am trying to work with the following design example. https://fpgacloud.intel.com/devstore/platform/18.1.0/Pro/pci-express-gen3-x16-avmm-dma-with-hbm2-memory-reference-design/ I am ab...
Pramod_atintel's avatar
Pramod_atintel
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4 years ago

Hi John,

Thanks for the reply.

I was able to solve the issue by assigning the correct pin numbers to reference clocks of HBM.

I was able to build the Qsys design with MCDMA IP interfaced with HBM Controller through AXI bridge. ( I have modified the example design PCIe + DDR + HBM2. I have replaced PCIe endpoint IP with MCDMA IP).

https://fpgacloud.intel.com/devstore/platform/19.1.0/Pro/an881-pcie-avmm-dma-gen3x16-ddr4-and-hbm2/

I am able to build and program the design successfully using Quartus 21.3 version.

During software test, system is not able to work with burstcount greater than 1. I have enabled burstcount greater than 1 option during HBM Controller generation. I have given it as 128 (max is 256).

Does HBM controller with AXI interface works with burst count greater than 1 ?

Best Regards,

Pramod